Verilog specifications

Implement combinational logic that arbitrates automatic and manual heating, cooling, and fan commands.

IndustryEmbedded

8-to-3 Priority Encoder

Encode eight requests into a three-bit index with fixed priority and a validity flag.

EmbeddedIndustry

BCD-to-7-segment Decoder

Convert a BCD digit into active-high controls for a 7-segment display with priority blanking.

EmbeddedIndustry

12-bit Unsigned Adder-subtractor

Build a combinational arithmetic unit with addition overflow and subtraction underflow detection.

MathEmbedded

Dead-band Thermostat

Control a heater and cooler around a target using a five-degree dead band.

IndustryEmbedded

Three-input Boolean Circuit

Verilog

Translate a Boolean expression into a combinational network.

Complete Dead-band Thermostat

Inkjet Bus Decoder

Verilog

Decode a nozzle number into a safe one-hot command.

Complete Three-input Boolean Circuit

Fail-safe Traffic-light Decoder

Verilog

Decode a one-hot state and force red for every invalid code.

Complete Inkjet Bus Decoder

Traffic-light Enable Gate

Verilog

Add a global enable to traffic-light commands.

Complete Fail-safe Traffic-light Decoder

3-bit 2-to-1 Multiplexer

Verilog

Select one of two three-bit words.

Complete Traffic-light Enable Gate

Active-low Night Light

Verilog

Drive an active-low lamp from daylight and an active-low enable.

Complete 3-bit 2-to-1 Multiplexer

8-bit Adder with Carry

Verilog

Add two bytes and a carry-in without losing the ninth bit.

Complete Active-low Night Light

4-bit Magnitude Comparator

Verilog

Compare two unsigned numbers with three mutually exclusive flags.

Complete 8-bit Adder with Carry

Parity Generator and Checker

Verilog

Generate an even-parity bit and detect an invalid parity frame.

Complete 4-bit Magnitude Comparator

D Flip-flop with Asynchronous Reset

Verilog

Store one bit on rising edges with a priority asynchronous reset.

Complete Parity Generator and Checker

8-bit Register with Enable

Verilog

Load or retain one byte according to an enable signal.

Complete D Flip-flop with Asynchronous Reset

Serial-in Parallel-out Shift Register

Verilog

Assemble eight serially received bits into a parallel register.

Complete 8-bit Register with Enable

Ripple-carry Adder

Verilog

Build a four-bit adder from four full adders.

Complete Serial-in Parallel-out Shift Register

Adder-subtractor with Overflow

Verilog

Perform signed addition and subtraction with carry and overflow flags.

Complete Ripple-carry Adder

4-bit Unsigned Multiplier

Verilog

Compute the full product of two four-bit unsigned numbers.

Complete Adder-subtractor with Overflow

Two-digit BCD Adder

Verilog

Add two BCD numbers from 00 to 99 with a decimal carry.

Complete 4-bit Unsigned Multiplier

PAL-style Address Decoder

Verilog

Decode three memory regions and report forbidden transactions.

Complete Two-digit BCD Adder

Four-digit BCD Sanitizer

Verilog

Validate every BCD nibble and block illegal words. Implement every specified decision.

Complete PAL-style Address Decoder

Eight-bit Thermometer Decoder

Verilog

Convert a contiguous run of LSB ones into binary. Implement every specified decision.

Complete Four-digit BCD Sanitizer

Eight-bit Saturating Adder

Verilog

Add two bytes without allowing wraparound. Implement every specified decision.

Complete Eight-bit Thermometer Decoder

BCD Magnitude Comparator

Verilog

Compare two BCD numbers after validation. Implement every specified decision.

Complete Eight-bit Saturating Adder

Five-input Majority Voter

Verilog

Take a majority decision across five redundant channels. Implement every specified decision.

Complete BCD Magnitude Comparator

One-hot Vector Analyzer

Verilog

Verify that exactly one bit is active and return its index. Implement every specified decision.

Complete Five-input Majority Voter

Leading-one Detector

Verilog

Locate the most-significant active bit. Implement every specified decision.

Complete One-hot Vector Analyzer

Programmable Address Window

Verilog

Decode an address between two inclusive bounds. Implement every specified decision.