Verilog specifications

Sequence datapath selects, partial-product enables, and result writes across five states for complex multiplication.

MathDSP

Complex Multiplier Datapath

Combinationally compute the product of two signed complex numbers.

Iterative 8 x 8 Multiplier

Multiply two bytes in eight cycles using shifts and additions.

Iterative Restoring Divider

Compute an unsigned quotient and remainder in eight iterations.

8-bit ALU with Flags

Combine eight arithmetic and logic operations with status flags.

4 x 4 Matrix Keypad Scanner

Verilog

Scan four rows and encode the detected key.

Complete 8-bit ALU with Flags

8N1 UART Transmitter

Verilog

Serialize one byte with a start bit, eight data bits, and a stop bit.

Complete 4 x 4 Matrix Keypad Scanner

8N1 UART Receiver

Verilog

Sample an 8N1 serial frame and report invalid stop bits.

Complete 8N1 UART Transmitter

PS/2 Receiver

Verilog

Receive a PS/2 keyboard frame and check its start, parity, and stop bits.

Complete 8N1 UART Receiver

VGA Synchronization Generator

Verilog

Generate pixel counters, visible area, and parameterized synchronization pulses.

Complete PS/2 Receiver

Fixed-priority Bus Arbiter

Verilog

Grant a bus to one requester at a time and hold the grant until release.

Complete VGA Synchronization Generator

3 x 3 Sobel Operator

Verilog

Compute a gradient-magnitude approximation over a nine-pixel window.

Complete Fixed-priority Bus Arbiter

Asynchronous SRAM Controller

Verilog

Turn an internal request into a timed asynchronous SRAM read or write cycle.

Complete 3 x 3 Sobel Operator

Burst DMA Controller

Verilog

Copy a sequence of words between two address spaces with separate handshakes.

Complete Asynchronous SRAM Controller

Direct-mapped Cache Controller

Verilog

Cache four words and refill one line on a miss.

Complete Burst DMA Controller

Digital PLL Loop Filter

Verilog

Integrate lead and lag events from a digital phase detector.

Complete Direct-mapped Cache Controller

DRAM Refresh Decision Unit

Verilog

Arbitrate between normal access and overdue refresh. Implement every specified decision.

Complete Digital PLL Loop Filter

Fast-page DRAM Command

Verilog

Detect an open-row hit and select RAS/CAS. Implement every specified decision.

Complete DRAM Refresh Decision Unit

Urgent Memory Arbiter

Verilog

Prioritize urgent requests, then apply rotation. Implement every specified decision.

Complete Fast-page DRAM Command

Cache Write-policy Unit

Verilog

Decide hit, allocation, or write-back. Implement every specified decision.

Complete Urgent Memory Arbiter

DMA Descriptor Address

Verilog

Compute an indexed descriptor address. Implement every specified decision.

Complete Cache Write-policy Unit

Binary16 Floating-point Classifier

Verilog

Classify zero, subnormal, normal, infinity, and NaN. Implement every specified decision.