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Write synthesizable Verilog and validate each module with a self-checking testbench run by Icarus Verilog.
0/27 exercises completed
Schedule the five steps of a complex product
VerilogDescribe the sequence that selects operands, enables partial products, and writes the real and imaginary results.
Complex Multiplier Datapath
VerilogCombinationally compute the product of two signed complex numbers.
Iterative 8 x 8 Multiplier
VerilogMultiply two bytes in eight cycles using shifts and additions.
Iterative Restoring Divider
VerilogCompute an unsigned quotient and remainder in eight iterations.
8-bit ALU with Flags
VerilogCombine eight arithmetic and logic operations with status flags.
4 x 4 Matrix Keypad Scanner
VerilogScan four rows and encode the detected key.
Complete 8-bit ALU with Flags
8N1 UART Transmitter
VerilogSerialize one byte with a start bit, eight data bits, and a stop bit.
Complete 4 x 4 Matrix Keypad Scanner
8N1 UART Receiver
VerilogSample an 8N1 serial frame and report invalid stop bits.
Complete 8N1 UART Transmitter
PS/2 Receiver
VerilogReceive a PS/2 keyboard frame and check its start, parity, and stop bits.
Complete 8N1 UART Receiver
VGA Synchronization Generator
VerilogGenerate pixel counters, visible area, and parameterized synchronization pulses.
Complete PS/2 Receiver
Fixed-priority Bus Arbiter
VerilogGrant a bus to one requester at a time and hold the grant until release.
Complete VGA Synchronization Generator
3 x 3 Sobel Operator
VerilogCompute a gradient-magnitude approximation over a nine-pixel window.
Complete Fixed-priority Bus Arbiter
Asynchronous SRAM Controller
VerilogTurn an internal request into a timed asynchronous SRAM read or write cycle.
Complete 3 x 3 Sobel Operator
Burst DMA Controller
VerilogCopy a sequence of words between two address spaces with separate handshakes.
Complete Asynchronous SRAM Controller
Direct-mapped Cache Controller
VerilogCache four words and refill one line on a miss.
Complete Burst DMA Controller
Digital PLL Loop Filter
VerilogIntegrate lead and lag events from a digital phase detector.
Complete Direct-mapped Cache Controller
DRAM Refresh Decision Unit
VerilogArbitrate between normal access and overdue refresh. Implement every specified decision.
Complete Digital PLL Loop Filter
Fast-page DRAM Command
VerilogDetect an open-row hit and select RAS/CAS. Implement every specified decision.
Complete DRAM Refresh Decision Unit
Urgent Memory Arbiter
VerilogPrioritize urgent requests, then apply rotation. Implement every specified decision.
Complete Fast-page DRAM Command
Cache Write-policy Unit
VerilogDecide hit, allocation, or write-back. Implement every specified decision.
Complete Urgent Memory Arbiter
DMA Descriptor Address
VerilogCompute an indexed descriptor address. Implement every specified decision.
Complete Cache Write-policy Unit
Binary16 Floating-point Classifier
VerilogClassify zero, subnormal, normal, infinity, and NaN. Implement every specified decision.
Complete DMA Descriptor Address
Parallel Register with Scan Chain
VerilogAdd a serial test-shift mode to a parameterized parallel register.
Complete Binary16 Floating-point Classifier
Logic BIST Controller
VerilogGenerate fifteen patterns from a 4-bit LFSR and compact the circuit-under-test responses.
Complete Parallel Register with Scan Chain
March Memory Test Controller
VerilogTest a 16-byte RAM by writing and reading back two complementary patterns.
Complete Logic BIST Controller
SECDED Code for 8 Bits
VerilogEncode eight bits with an extended Hamming code and correct a single-bit error.
Complete March Memory Test Controller
Distributed-Arithmetic FIR Filter
VerilogImplement a four-tap signed FIR using a lookup table and serial accumulator.
Complete SECDED Code for 8 Bits