Specification

Design a four-bit synchronous counter that advances from 0 through 9 and then wraps to zero.

EmbeddedIndustry

10-bit Down-counter Timer

Load a duration, decrement it every cycle, and flag zero before arithmetic wraparound.

EmbeddedReal-time

Reloading Periodic Timer

Store a period, count down to zero, and then automatically reload the programmed value.

EmbeddedReal-time

Parameterized Counter

Create a counter whose width is selected at instantiation.

Digital logicFPGA

4-bit Up-down Counter

Count in both directions with enable and modulo-sixteen wraparound.

Digital logicFPGA

Modulo-12 Counter

Verilog

Count from zero through eleven and pulse on wraparound.

Complete 4-bit Up-down Counter

Pulse Stretcher

Verilog

Turn a one-cycle pulse into an active level of a fixed duration.

Complete Modulo-12 Counter

Switch Debouncer

Verilog

Filter unstable transitions on an asynchronous input.

Complete Pulse Stretcher

16 x 8 Asynchronous-read RAM

Verilog

Model a small memory with synchronous write and combinational read.

Complete Switch Debouncer

16 x 8 Synchronous-read RAM

Verilog

Model a RAM whose read and write operations occur on rising edges.

Complete 16 x 8 Asynchronous-read RAM

Dual-read Register File

Verilog

Build an eight-register file with one write and two simultaneous reads.

Complete 16 x 8 Synchronous-read RAM

8 x 8 Synchronous FIFO

Verilog

Implement an eight-byte queue with empty and full flags.

Complete Dual-read Register File

Seven-segment Decoder ROM

Verilog

Use a combinational lookup table to display a hexadecimal digit or blank the display.

Complete 8 x 8 Synchronous FIFO

Single-digit BCD Adder

Verilog

Add two BCD decimal digits and a carry-in.

Complete Seven-segment Decoder ROM

Barrel Shifter and Rotator

Verilog

Shift or rotate a byte by zero through seven positions in one combinational cycle.

Complete Single-digit BCD Adder

1011 Sequence Detector

Verilog

Detect an overlapping serial sequence with a Mealy state machine.

Complete Barrel Shifter and Rotator

Programmable Timer

Verilog

Load a period and produce a pulse after the requested number of cycles.

Complete 1011 Sequence Detector

Hamming (7,4) Code

Verilog

Encode four bits and automatically correct one single-bit error.

Complete Programmable Timer

LFSR Stream Cipher

Verilog

Combine each byte with a reproducible pseudo-random sequence.

Complete Hamming (7,4) Code

One’s-complement Checksum

Verilog

Compute the checksum of packets made of sixteen-bit words.

Complete LFSR Stream Cipher

PS/2 Mouse Packet Decoder

Verilog

Assemble three PS/2 bytes into buttons and signed movements.

Complete One’s-complement Checksum

Blackjack Score Engine

Verilog

Compute the best value of a five-card hand without exceeding 21.

Complete PS/2 Mouse Packet Decoder

PRBS Sequence Checker

Verilog

Compute the next LFSR state and count mismatches. Implement every specified decision.

Complete Blackjack Score Engine

SRAM Byte-lane Mapper

Verilog

Merge one byte according to two byte enables. Implement every specified decision.

Complete PRBS Sequence Checker

PS/2 Frame Validator

Verilog

Check start, stop, and odd parity. Implement every specified decision.

Complete SRAM Byte-lane Mapper

Reciprocal Frequency Estimator

Verilog

Divide a reference count by a measured period. Implement every specified decision.

Complete PS/2 Frame Validator

Windowed Watchdog Decision

Verilog

Classify a kick as early, valid, or late. Implement every specified decision.

Complete Reciprocal Frequency Estimator

Eight-request Rotating Arbiter

Verilog

Select the first request after the previous winner. Implement every specified decision.

Complete Windowed Watchdog Decision

BCD Digit Multiplier

Verilog

Multiply two BCD digits and produce a two-digit BCD result.

Complete Eight-request Rotating Arbiter

BCD Decimal Divider

Verilog

Divide a two-digit BCD value by one BCD digit and return quotient and remainder.

Complete BCD Digit Multiplier

VGA Digit Character ROM

Verilog

Generate decimal-digit pixels from a character code and a position in an 8×8 cell.

Complete BCD Decimal Divider

PDM Counter Decimator

Verilog

Measure the bit density of a PDM stream over 16-sample windows.

Complete VGA Digit Character ROM

Single-Entry AXI-Stream Buffer

Verilog

Buffer one AXI-Stream byte and handle backpressure without losing data.

Complete PDM Counter Decimator

SPI Mode 0 Master

Verilog

Transmit and receive one SPI mode 0 byte with a configurable clock divider.

Complete Single-Entry AXI-Stream Buffer

Five-Tap FIR Filter

Verilog

Compute a five-tap FIR output for each valid input sample.

Complete SPI Mode 0 Master

Four-Source Interrupt Controller

Verilog

Latch four requests and report the highest-priority enabled request.

Complete Five-Tap FIR Filter

Serial CRC-16/CCITT-FALSE Calculator

Verilog

Update a CRC-16/CCITT value from an MSB-first serial stream.

Complete Four-Source Interrupt Controller

8-bit Carry-Lookahead Adder

Verilog

Add two bytes using carry lookahead grouped into four-bit blocks.