4-bit Johnson Counter

On each rising edge of clk, shift q toward the least-significant bits and feed the inverted outgoing bit into bit 3.

Behavior

• reset is synchronous and active high; it loads q=0.
• Without reset, the sequence is 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, then repeats.
• Asserting reset between clock edges does not immediately change q.