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10-bit Down-counter Timer

Intermediate

Simulate (Icarus Verilog)

00:00

Specification

01Operation

The timer uses a 10-bit unsigned counter.

Behavior

reset=1 immediately forces count to 0.
When load=1 on a rising edge, data is loaded into count.
Otherwise, count decrements on each rising edge.
tc is 1 whenever count is 0.
Decrementing from 0 produces 1023 by unsigned wraparound.

Reset is asynchronous, while loading is synchronous.

02Interface

Signal	Direction	Width	Description
`clk`, `reset`, `load`	Input	1 bit	Control
`data`	Input	10 bits	Load value
`count`	Output	10 bits	Current value
`tc`	Output	1 bit	Counter is zero

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