Chargement…
Chargement…
A new pulse restarts the timing interval.
Behavior
pulse_in=1, active remains 1 for HOLD_CYCLES cycles.reset=1 cancels timing at the next edge.| Signal | Direction | Width | Description |
|---|---|---|---|
clk, reset, pulse_in | Input | 1 bit | Clock, reset, and pulse |
active | Output | 1 bit | Stretched level |