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Single-digit BCD Adder

Intermediate

Simulate (Icarus Verilog)

00:00

Specification

01Operation

An add-six correction turns the binary sum into valid BCD.

Behavior

Inputs a and b range from 0 through 9.
If the sum exceeds 9, add 6 and assert carry_out.

02Interface

Signal	Direction	Width	Description
`a, b`	Input	4 bits	BCD digits
`carry_in`	Input	1 bit	Decimal carry-in
`sum`	Output	4 bits	Result BCD digit
`carry_out`	Output	1 bit	Decimal carry-out

← Seven-segment Decoder ROM