Four-Source Interrupt Controller

On each rising edge, bits in requests are latched into pending. A new request takes priority over clearing the same bit.

• Synchronous active-high reset clears all requests.
• clear clears the bit selected by clear_id.
• mask enables the corresponding sources. Among enabled pending requests, index 0 has highest priority.
• irq is 1 when any enabled request is pending; irq_id reports its index. With no enabled request, irq=0 and irq_id=0.