>_FPGA Pour Tous Blog

Blog Careers Challenges Leaderboard Community Certification Projects The Club

Chargement…

>_FPGA Pour Tous

Learn VHDL, from beginner to expert.

Courses

VHDL
Verilog
SystemVerilog
FPGA
Hardware and PCB
Digital Electronics
Protocols
Zynq

Practice

All exercises
HW to simulation
VHDL specifications
Verilog specifications
Software to schematic
Block Design
Leaderboard
Report a bug

Blog

FPGA & VHDL articles
Challenges
Certification
Community
FAQ

© 2026 FPGA Pour Tous

FAQ|Legal|Privacy|Terms

LFSR Byte Whitener

Intermediate

Simulate (Icarus Verilog)

00:00

Advance the PRBS and XOR its low byte. Reproduce the schematic datapath exactly.

Schematic

Structural schematic

Scroll: zoom

← Modulo-60 Time Datapath