Verilog Hardware → Simulation

Recreate the combinational datapath that increments a BCD value from 00 to 99.

Digital logicEmbedded

Dual-priority Encoder

Identify the two highest-priority active requests in an eight-bit vector.

Digital logicIndustry

Open-drain Bus Resolver

Model four open-drain outputs connected to a shared pull-up resistor.

I/OEmbedded

Single-digit BCD Subtractor

Subtract two decimal digits with borrow. Implement every specified decision.

MathDigital logic

Balanced Parity Tree

Compute four local parities and then global parity. Implement every specified decision.

TelecomDigital logic

Symmetric Window Detector

Verilog

Compare an absolute difference against a tolerance. Implement every specified decision.

Complete Balanced Parity Tree

End-around-carry Adder

Verilog

Feed carry-out back into the sixteen-bit sum. Implement every specified decision.

Complete Symmetric Window Detector

One-hot Grant Encoder

Verilog

Turn eight requests into a one-hot grant. Implement every specified decision.

Complete End-around-carry Adder

Binary-to-Gray Datapath

Verilog

Convert a binary word into Gray code. Implement every specified decision.