Verilog Hardware → Simulation

Implement the three-master cyclic arbiter shown by the state diagram.

IndustryProcessor

Blackjack Dealer FSM

Recreate the state machine that requests cards until reaching at least 17.

Digital logicConsumer

Digital Alarm-clock Controller

Recreate the hour/minute registers and alarm trigger logic.

EmbeddedConsumer

PS/2 Frame Datapath

Extract and validate a PS/2 byte. Implement every specified decision.

I/OEmbedded

Programmable Divider Phase

Compute the next phase and toggle event. Implement every specified decision.

ClockingSensors

SRAM Read-cycle Decoder

Verilog

Derive CE, OE, and ready from phase. Implement every specified decision.

Complete Programmable Divider Phase

Modulo-60 Time Datapath

Verilog

Increment seconds and minutes with carry. Implement every specified decision.

Complete SRAM Read-cycle Decoder

LFSR Byte Whitener

Verilog

Advance the PRBS and XOR its low byte. Implement every specified decision.

Complete Modulo-60 Time Datapath

Blackjack Hand Datapath

Verilog

Score four cards and adjust aces. Implement every specified decision.