Verilog Hardware → Simulation

Recreate a pulse-mode machine in which each event pulse triggers one atomic transition.

IndustryControl

Wait-state Bus Master

Recreate the master that holds a transaction until the slave is ready.

ProcessorI/O

VeSPA Pipeline Hazard Unit

Recreate the comparators and forwarding multiplexers of a processor pipeline.

ProcessorFPGA

Strided DMA Address Generator

Compute base plus index times a stride. Implement every specified decision.

MemoryProcessor

Direct-mapped Cache Tag Lookup

Split tag, index, and offset, then validate a hit. Implement every specified decision.

MemoryProcessor

DRAM Row-column Multiplexer

Verilog

Alternately present row and column. Implement every specified decision.

Complete Direct-mapped Cache Tag Lookup

PLL Lock-window Filter

Verilog

Update a counter according to phase error. Implement every specified decision.

Complete DRAM Row-column Multiplexer

VeSPA Branch Flush Control

Verilog

Choose next PC and flush commands. Implement every specified decision.

Complete PLL Lock-window Filter

BIST Signature Analyzer

Verilog

Mix a response into a polynomial signature. Implement every specified decision.