AD9832 DDS Controller

Specification

General Operation

The module programs the AD9832 DDS using the provided SPI master.

It initializes the device, writes a 32-bit frequency word in 8-bit chunks, and then alternates between the two frequency registers.

Behavior

After i_reset_n='0', the power-up sequence places the AD9832 in reset, clears the four frequency-register bytes, and then releases reset.
i_spi_top='1' latches i_data_to_send while the controller is idle.
The FSM then sends four 16-bit commands for the four frequency-word bytes, followed by the configuration and selection commands used in the supplied solution.
After each programming sequence, the controller alternates between the FREQ0 and FREQ1 registers.
io_ss_n(0), io_sclk, and o_mosi connect to the AD9832 FSYNC, SCLK, and SDATA pins, respectively.

Generics2

g_CLK_FREQ_MHZ: Type :integerDefault :40Description :Nominal i_clk frequency in MHz, retained in the supplied solution interface
g_DIV: Type :integerDefault :1Description :Divider parameter retained in the supplied solution interface

Ports7

Port	Direction	Width	Description
`i_clk`	Input	1 bit	Controller system clock
`i_reset_n`	Input	1 bit	Active-low reset
`i_spi_top`	Input	1 bit	Pulse requesting programming of a new frequency word
`i_data_to_send`	Input	32 bits	AD9832 frequency word split across the four bytes of the selected register
`io_ss_n`	Input/Output	1 bit	Serial select connected to AD9832 `FSYNC`
`io_sclk`	Input/Output	1 bit	Serial clock connected to AD9832 `SCLK`
`o_mosi`	Output	1 bit	Serial data connected to AD9832 `SDATA`

Refer to the official AD9832 documentation for command encoding, the four frequency-byte addresses, and the reset sequence.

Chargement…