Chargement…
Chargement…
8-bit register combining parallel load and left shift. Loading copies input data into the register. Shifting outputs the MSB through o_msb and inserts '0' at the LSB. Load has priority over shift.
Reset is asynchronous and active-high.
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
i_load | Input | 1 bit | Parallel load |
i_shift | Input | 1 bit | Left shift |
i_data | Input | 8 bits | Parallel data |
o_msb | Output | 1 bit | Most significant bit |
o_reg | Output | 8 bits | Register content |