4-Bit Left Shift Register

Beginner

00:00

01General Operation

4-bit left shift register. Bits advance one position to the left on each clock cycle.

Behaviour:

Reset (i_reset='1'): o_q ← "0000", o_sout ← '0'.
Rising edge of i_clk: left shift, i_sin enters at the LSB, the leaving MSB is exposed on o_sout.
o_q continuously reflects the 4 flip-flop states.

*Asynchronous active-high reset.*

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_reset`	Input	1 bit	Active-high async reset
`i_sin`	Input	1 bit	Serial input (enters at LSB)
`o_sout`	Output	1 bit	Serial output (MSB)
`o_q`	Output	4 bits	Register content

Chargement…