Chargement…
Chargement…
4-bit left shift register. On each rising edge, bits shift one position left: serial input enters at the LSB and the MSB exits through o_sout. Reset clears to "0000".
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
i_sin | Input | 1 bit | Serial input (enters at LSB) |
o_sout | Output | 1 bit | Serial output (MSB) |
o_q | Output | 4 bits | Register content |