Chargement…
Chargement…
4-bit serial-in parallel-out (SIPO) register. On each rising edge, a bit enters serially and shifts the others. After 4 cycles, the 4 serialized bits are available in parallel. Reset clears to "0000".
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
i_sin | Input | 1 bit | Serial input (enters at MSB) |
o_q | Output | 4 bits | Parallel output |