4-Bit SIPO Shift Register

Beginner

00:00

01General Operation

4-bit serial-in parallel-out (SIPO) register. After 4 clock edges, the user has serialised a 4-bit word now available in parallel on o_q.

Behaviour:

Reset (i_reset='1'): o_q ← "0000".
Rising edge of i_clk: right shift; i_sin enters at the MSB, the old LSB is dropped.
o_q is wired combinationally to the 4 flip-flops' current state.

*Asynchronous active-high reset.*

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_reset`	Input	1 bit	Active-high async reset
`i_sin`	Input	1 bit	Serial input (enters at MSB)
`o_q`	Output	4 bits	Parallel output

Chargement…