AXI4 Master — Read Channels

Intermediate

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01General Operation

AXI4 single-beat read master. The rising edge of i_read_go triggers a read transaction at address i_address. The module manages AR (address) and R (data) channels using the AXI4 VALID/READY handshake. Read data is available on o_data_out with a pulse on o_rd_done.

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_rst`	Input	1 bit	Synchronous reset
`i_read_go`	Input	1 bit	Read trigger (level)
`i_rd_addr`	Input	32 bits	Read address
`o_rdata`	Output	32 bits	Read data
`o_rvalid`	Output	1 bit	Data valid
`o_rd_done`	Output	1 bit	Read done pulse
`m_axi_araddr`	Output	32 bits	AXI Read Address
`m_axi_arvalid`	Output	1 bit	AXI AR Valid
`m_axi_arready`	Input	1 bit	AXI AR Ready
`m_axi_rdata`	Input	32 bits	AXI Read Data
`m_axi_rresp`	Input	2 bits	AXI Read Response
`m_axi_rlast`	Input	1 bit	AXI Read Last
`m_axi_rvalid`	Input	1 bit	AXI R Valid
`m_axi_rready`	Output	1 bit	AXI R Ready

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