AXI-Lite Slave — Register Map

Intermediate

00:00

01General Operation

The module exposes three 32-bit registers accessible via AXI4-Lite: REG_CTRL (0x00), REG_PERIOD (0x04), REG_GAIN (0x08). Two independent state machines handle write and read transactions per the AXI4-Lite protocol.

Register offsets: CTRL=0x00, PERIOD=0x04, GAIN=0x08
OKAY or SLVERR response depending on address validity

02Interface

Generics:

g_BASE_ADDR : std_logic_vector(31 downto 0) — Base address (default x"0000_0000")

AXI-Lite Ports:

Signal	Direction	Width	Description
`i_axi_aclk`	Input	1 bit	AXI clock
`i_axi_areset`	Input	1 bit	Synchronous reset
`s_axi_awaddr`	Input	32 bits	Write Address
`s_axi_awvalid`	Input	1 bit	AW Valid
`s_axi_awready`	Output	1 bit	AW Ready
`s_axi_wdata`	Input	32 bits	Write Data
`s_axi_wstrb`	Input	4 bits	Write Strobe
`s_axi_wvalid`	Input	1 bit	W Valid
`s_axi_wready`	Output	1 bit	W Ready
`s_axi_bresp`	Output	2 bits	Write Response
`s_axi_bvalid`	Output	1 bit	B Valid
`s_axi_bready`	Input	1 bit	B Ready
`s_axi_araddr`	Input	32 bits	Read Address
`s_axi_arvalid`	Input	1 bit	AR Valid
`s_axi_arready`	Output	1 bit	AR Ready
`s_axi_rdata`	Output	32 bits	Read Data
`s_axi_rresp`	Output	2 bits	Read Response
`s_axi_rvalid`	Output	1 bit	R Valid
`s_axi_rready`	Input	1 bit	R Ready

Register Ports:

`o_reg_ctrl`	Output	32 bits	REG_CTRL value
`o_reg_period`	Output	32 bits	REG_PERIOD value
`o_reg_gain`	Output	32 bits	REG_GAIN value

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