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Bidirectional synchronous counter of configurable width. Supports parallel load (priority over counting), up or down counting based on i_dir, and signals overflow via o_wrap.
Reset is asynchronous and active-high.
g_width (default 8)| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_reset | Input | 1 bit | Active-high async reset |
i_en | Input | 1 bit | Counter enable |
i_dir | Input | 1 bit | Direction (1=up, 0=down) |
i_load | Input | 1 bit | Parallel load |
i_data | Input | g_width bits | Data to load |
o_cpt | Output | g_width bits | Counter value |