8x8 Dual-Port RAM

Intermediate

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01General Operation

On rising edge, if i_we = '1', writes i_wdata at i_waddr. Read at i_raddr is asynchronous and independent from the write port.

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	Clock
`i_we`	Input	1 bit	Write enable
`i_waddr`	Input	3 bits	Write address
`i_wdata`	Input	8 bits	Write data
`i_raddr`	Input	3 bits	Read address
`o_rdata`	Output	8 bits	Read data

Chargement…