4x8 Register File

Intermediate

00:00

01General Operation

Synchronous write (rising edge) when i_we = '1'. Two independent asynchronous read ports. Reset clears all registers to 0.

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	Clock
`i_reset`	Input	1 bit	Active-high async reset
`i_we`	Input	1 bit	Write enable
`i_waddr`	Input	2 bits	Write address
`i_wdata`	Input	8 bits	Write data
`i_raddr1`	Input	2 bits	Read address port 1
`i_raddr2`	Input	2 bits	Read address port 2
`o_rdata1`	Output	8 bits	Read data port 1
`o_rdata2`	Output	8 bits	Read data port 2

Chargement…