Simple Full-Duplex UART

IntermediateChallenge

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01General Operation

The module exposes two independent channels sharing the same clock.

Behavior

TX transmitter: when i_send is asserted for one cycle, i_data is latched and transmitted on o_txd in 8N1 format: start bit '0', 8 data bits LSB first, stop bit '1'.
o_busy stays at '1' during the whole transmission.
RX receiver: detects the start bit on i_rxd, samples in the middle of each bit, then captures 8 bits LSB first.
If the stop bit is valid, o_data exposes the received byte and o_valid pulses for one cycle.

The i_rst reset is synchronous active-high. No parity, no flow control.

02Generics

Generic	Type	Default	Role
`g_CLK_FREQ`	`integer`	50_000_000	`i_clk` frequency in Hz
`g_BAUD_RATE`	`integer`	3_125_000	Target serial baud rate

One bit lasts g_CLK_FREQ / g_BAUD_RATE cycles. In the testbench, this ratio is 16 cycles.

03Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_rst`	Input	1 bit	Active-high synchronous reset
`i_rxd`	Input	1 bit	Serial RX line, idle at '1'
`o_txd`	Output	1 bit	Serial TX line, idle at '1'
`i_data`	Input	8 bits	Byte to transmit
`i_send`	Input	1 bit	One-cycle transmission request
`o_busy`	Output	1 bit	TX transmission in progress
`o_data`	Output	8 bits	Received byte
`o_valid`	Output	1 bit	`o_data` validation pulse

04Implementation Constraints

Implement two independent FSMs: one TX FSM and one RX FSM.
Suggested TX states: TX_IDLE, TX_START, TX_DATA, TX_STOP.
Suggested RX states: RX_IDLE, RX_START, RX_DATA, RX_STOP.
Sample RX in the middle of the start bit, then every bit period.
Follow the project naming conventions: i_, o_, r_, c_, g_, t_, P_.
The rtl architecture must remain synthesizable and must not infer latches.

Chargement…