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On each i_valid pulse, i_digit(3:0) is compared to the expected digit. Any mismatch goes to FAIL. Full sequence leads to OPEN. i_rst returns to initial state. Output o_open='1' in OPEN, o_fail='1' in FAIL.
i_valid
i_digit(3:0)
FAIL
OPEN
i_rst
o_open='1'
o_fail='1'