Chargement…
Chargement…
Engineering path
This path follows a real project from hardware to software. It connects the Block Design, XSA, BSP, C code, interrupts, DMA transfers, boot, debugging and Linux.
Prerequisites
FPGA, VHDL, C and AXI-Lite basics.
Method
Read, reproduce the code, measure, then verify.
Target
Zynq-7000 and Zynq UltraScale+ MPSoC.
Understand Zynq families, processors, memories and the interfaces between the PS and PL.
Understand the split between the Processing System and programmable logic in Zynq-7000 and Zynq UltraScale+ MPSoC devices.
Understand application and real-time processors, caches, address spaces and memory resources in a Zynq system.
Select AXI ports between the Processing System and programmable logic, then manage clocks, resets, interrupts and memory coherency.
Build the hardware in Vivado, export the XSA, create a Vitis platform and use the BSP.
Build a Zynq platform in IP Integrator, connect IP, assign addresses and export the hardware to Vitis.
Create a software platform, understand the BSP and control an AXI GPIO with low-level and high-level drivers.
Understand the embedded C library, BSP structure and the two driver levels used by a Vitis application.
Handle events with the GIC and move buffers efficiently with DMA.
Move from JTAG loading to a standalone image, then correlate processor execution with PL signals.
Create an AXI IP, integrate it into the BSP, verify it in simulation and use it from Linux.
Create an AXI-Lite peripheral, define its register map, package it and integrate a driver into the BSP.
Understand the kernel, user space, Device Tree and safe paths for accessing PL hardware.
Verify an AXI-Lite slave in simulation using a master agent, controlled transactions and protocol checks.
Build a Vitis platform step by step and control the ZCU104 LEDs from a serial terminal.