Write a testbench

Verify that the output is inverted for both input values.

Verify the negated product, especially the two-input-high case.

Verify the low output when an input is active and the high idle output.

Verify one-hot decoding and the enable behavior.

Verify less-than, equal and greater-than relations on representative values.

Verify even parity for zero, an odd value and a two-bit value.

Verify sum and carry for all four input pairs.

Verify sum and carry with and without an input carry.

Verify carries, zero operands and addition overflow.

Verify difference and borrow for subtractions with and without borrow.

Verify most-significant-bit priority and the no-request case.

Verify digits 0, 1, 8 and an out-of-range value.

Verify left and right shifts with discarded outgoing bits.

Verify asynchronous reset, capture and hold while enable is disabled.

Verify serial insertion and bit progression across several edges.

Verify that a one-cycle pulse appears only on a rising transition.

Verify rising-edge capture and hold when enable is low.

Verify reset, hold and wrap-around from zero to fifteen.

Verify the decimal sequence and return to zero after nine.

Verify the active-bit rotation and cyclic return.

Verify the pseudo-random sequence and the non-zero state after reset.

Verify that an input pulse produces the defined output duration.

Verify that an input remains stable for several cycles before acceptance.

Verify duty-cycle boundaries and ramp transitions.

Verify loading, countdown and the completion pulse.

Verify cyclic state transitions and reset to the initial state.

Verify overlapping detection and incomplete sequences.

Verify conditional addition, hold and modulo overflow.

Verify saturation at fifteen instead of wrap-around.

Verify zero, maximum and multi-bit transition values.

Verify zero, one active position and multiple active bits.

Verify the four-to-one and three-to-two thresholds.

Verify even, odd and extreme data words.

Verify clear priority over writes and the hold behavior.

Verify decisions on profiles close to the threshold.

Verify start bit, eight data bits and stop bit at the requested baud tick.

Verify clock edges, MSB-first order and transaction completion.

Verify timeout, service and alarm output.

Verify a fixed-width pulse and ignored triggers while active.

Verify acceptance latency and rejection of short changes.

Verify overlap, partial overlap and absence of false positives.

Verify CRC results on several words and reset between frames.

Verify priority, validity and transitions between multiple requests.

Verify read, write, addressing and reserved-address protection.

Verify asynchronous reset assertion and release after two clock edges.

Verify consume, return, boundary saturation and simultaneous events.

Verify start, counting, early end and correct length.

Verify division, reload and the exactly periodic pulse.

Verify writes, reads and independence of both ports.

Verify valid/ready, data hold and transaction completion.

Verify reset, loading, countdown and the completion pulse.

Verify rotating priority, one-hot grants and respect for backpressure.

Verify signed products, zero and representable boundaries.

Verify sum and difference reduction within the modulo interval.

Verify quotient, remainder and explicit division-by-zero behavior.