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Asynchronous SRAM Controller

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Simulate (Icarus Verilog)

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Specification

01Operation

The controller holds address, data, and strobes throughout all wait cycles.

Behavior

An accepted request is latched and raises busy.
Reads assert ce_n and oe_n low; writes assert ce_n and we_n low and data_oe high.
After WAIT_CYCLES, read data is captured and ready pulses for one cycle.

02Interface

Signal	Direction	Width	Description
`clk, reset, request, write`	Input	1 bit	Clock and command
`address, write_data`	Input	16 bits	Internal address and data
`read_data, busy, ready`	Output	16/1 bits	Internal response
`sram_address, sram_data_out`	Output	16 bits	Address and write data driven to SRAM
`sram_data_in`	Input	16 bits	Read data received from SRAM
`sram_ce_n, sram_oe_n, sram_we_n, sram_data_oe`	Output	1 bit	SRAM strobes

← 3 x 3 Sobel Operator