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Direct-mapped Cache Controller

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Simulate (Icarus Verilog)

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Specification

01Operation

Two bits select the line and upper address bits form the tag.

Behavior

The cache has four one-word lines indexed by cpu_address[3:2].
A hit returns data without a memory access and pulses cache_hit.
A miss holds memory_request until memory_ready, fills the line, then responds.

02Interface

Signal	Direction	Width	Description
`clk, reset, invalidate`	Input	1 bit	Clock and maintenance
`cpu_request, cpu_address`	Input	1/8 bits	CPU request
`cpu_data, cpu_ready, cache_hit`	Output	32/1 bits	CPU response
`memory_request, memory_address`	Output	1/8 bits	Memory request
`memory_ready, memory_data`	Input	1/32 bits	Memory response

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