Chargement…
Chargement…
Counter decade_counter is clocked on the rising edge of clk.
Behavior
reset=1 immediately forces q to 0.q increments on every rising edge.Reset is asynchronous and active high.
| Signal | Direction | Width | Description |
|---|---|---|---|
clk | Input | 1 bit | Clock |
reset | Input | 1 bit | Active-high asynchronous reset |
q | Output | 4 bits | BCD value from 0 through 9 |