Verilog

Modules, combinational and sequential logic, synthesis and testbenches in Verilog.

1. 01Understanding VerilogWhat Verilog is used for, how it describes a circuit, and where it fits in an FPGA project.Read
2. 02Modules, ports, and hierarchyDeclare an interface, choose between wire and reg, then connect several modules cleanly.Read
3. 03Literals, vectors, and operatorsWrite unambiguous constants, manipulate bits, and avoid width and signedness pitfalls.Read
4. 04Describing combinational logicUse assign and always @* to produce an output that depends only on the current inputs.Read
5. 05Describing sequential logicCreate clocked registers, handle reset and enable, and understand nonblocking assignments.Read
6. 06Conditions, case, and unintended latchesWrite complete choices, make priorities visible, and avoid storage created by omission.Read
7. 07Parameters, localparam, and generateMake a module reusable without turning its internal settings into hardware inputs.Read
8. 08Functions, tasks, and loopsFactor out a calculation, write synthesizable loops, and keep RTL separate from test utilities.Read
9. 09State machines in VerilogTurn a state diagram into readable, complete RTL that is easy to verify.Read
10. 10ROM, RAM, and FIFODescribe memories that tools can recognize and handle FIFO boundaries correctly.Read
11. 11Testbenches and schedulingApply clean stimulus, check outputs automatically, and understand when registers change.Read
12. 12Synthesis, timing, and RTL readingConnect source code to the resulting circuit, read latency, and fix an overly long path.Read