Clock, Reset, Configuration, and JTAG

Organize board startup around a stable clock and a known state.

Clock

An external clock must provide the expected frequency and electrical level. It must remain stable across supply, temperature, and time changes. Jitter is the timing variation of clock edges. It reduces available margin when an interface or logic path requires precise edge placement.

Internal clock managers can multiply, divide, or phase-shift a clock and may reduce some variations. They need time to lock, so their locked output belongs in the startup logic.

Reset

Reset puts the system in a known state, especially at power-up. It may come from a dedicated circuit, a supply supervisor, or a manual command. A sound sequence keeps reset asserted while rails, clock, and configuration are not ready.

Asynchronous assertion can react without a clock. Deassertion is often synchronized in each clock domain to prevent a reset edge from arriving at an unsafe point relative to that clock.

Configuration and JTAG

FPGA logic must be configured before it performs its function. Mode pins, configuration memory, and status signals determine the startup path.

JTAG forms a serial chain through compatible devices. It supports board connection testing and may also help with configuration or debug. Check chain order, connector access, electrical levels, and recommended bias resistors.

Debug order

1. Valid rails.
2. Present and stable clock.
3. Reset held and then released correctly.
4. Correct configuration mode.
5. Consistent configuration status signals.
6. Detectable JTAG chain.

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