I/O Banks and Logic Levels
Check VIL, VIH, VOL, VOH, current, and compatibility between two devices.
A logic pin is still an electrical device
Logic 0 and 1 are voltage bands, not two perfect values. Four limits define a digital connection:
VIL: highest input voltage still recognized as0.VIH: lowest input voltage recognized as1.VOL: highest output voltage produced for0.VOH: lowest output voltage produced for1.
A connection is compatible when the low output stays below VIL and the high output stays above VIH under the intended load.
Noise margins
Static margins are:
NML = VIL - VOL
NMH = VOH - VIH
A positive margin gives room for noise and voltage drop. Low-voltage systems often have less margin, so routing and power quality matter more.
Current and load
Output levels depend on sourced or sunk current. Read IOH and IOL together with the load conditions used for VOH and VOL. Counting connected inputs alone is not enough.
FPGA banks
FPGA I/Os are grouped into banks powered by a common voltage. Before assigning a pin:
- check the bank voltage;
- check that the I/O standard is available in that bank;
- separate incompatible interfaces or add level translation;
- review reserved, clock, and configuration pins;
- define a safe state for unused pins.
An input must not be left floating. Use the device's intended internal bias or a suitable external resistor.
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