Stackup, Vias, and BGA Routing

Plan board layers and escape a dense package without breaking signal references.

The stackup is an electrical definition

The stackup describes the order of copper and dielectric layers, their thickness, and their role. It determines the geometry available for controlled impedance and return paths.

A common arrangement places signal layers close to continuous planes. The final choice depends on rail count, density, impedance needs, and manufacturer rules.

Vias

A via changes layers but adds a discontinuity. For a fast signal, review:

• traversed length;
• unused via section;
• reference-plane change;
• distance to a return via;
• symmetry within a differential pair.

Power vias connect pins and capacitors to planes. Their count and placement affect power-network inductance.

Escaping a BGA

A BGA package concentrates many connections. Work starts before routing:

1. Group signals by bank, voltage, and function.
2. Reserve clocks, transceivers, configuration, and power pins.
3. Place capacitors and their vias early.
4. Select an escape method compatible with ball pitch and manufacturing rules.
5. Keep fast groups on consistent layers and references.
6. Reflect every pin-assignment change in FPGA constraints.

Pin assignment and board routing affect each other. A late change may move several traces and break a pair or I/O bank.

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