Testbenches and scheduling

Testbenches and scheduling

Apply clean stimulus, check outputs automatically, and understand when registers change.

A testbench is not RTL

A testbench has no ports. It instantiates the circuit, creates the clock, drives inputs, and decides whether the result is correct.

`timescale 1ns/1ps
 
module edge_counter (
  input  wire       i_clk,
  input  wire       i_reset,
  input  wire       i_enable,
  output reg  [3:0] o_count
);
 
  always @(posedge i_clk) begin
    if (i_reset)
      o_count <= 4'd0;
    else if (i_enable)
      o_count <= o_count + 1'b1;
  end
 
endmodule
 
module tb_edge_counter;