Synthesis, timing, and RTL reading

Connect source code to the resulting circuit, read latency, and fix an overly long path.

Synthesis does not verify intent

A synthesis tool turns RTL into registers, logic, and memories. It can accept code that does not meet the specification. Simulation, lint, constraints, and report review answer different questions.

Before optimizing, check:

• the width and signedness of every calculation;
• the absence of unintended latches;
• the presence of expected registers;
• the inference of intended RAM and DSP resources;
• warnings about undriven, constant, or truncated signals.

An RTL delay does not fix timing

Writing #2 in RTL does not ask the FPGA to make a path faster. Simulation delays are not a portable synthesizable architecture.

To shorten an overly long combinational path, you can:

• add a pipeline stage;
• reorganize a calculation as a tree;
• perform less shared logic in one cycle;
• use a dedicated resource;
• revisit the frequency or protocol if the specification allows it.

Reading a small pipeline

module pipelined_sum4 #(
  parameter WIDTH = 12
) (
  input  wire                 i_clk,
  input  wire                 i_reset,
  input  wire                 i_valid,
  input  wire [WIDTH-1:0]     i_a,
  input  wire [WIDTH-1:0]     i_b,
  input  wire [WIDTH-1:0]     i_c,
  input  wire [WIDTH-1:0]     i_d,
  output reg                  o_valid,
  output reg  [WIDTH+1:0]     o_sum
);
 
  reg [WIDTH:0

On the first edge, the two partial sums are registered. On the following edge, their sum is registered in o_sum, and o_valid carries the matching i_valid. Nonblocking assignments ensure that the second calculation uses the previous pair_ab and pair_cd values, not the values computed on that same edge.

The block can accept a new group of four operands every cycle. Its latency therefore does not prevent a throughput of one result per cycle once the pipeline is full.

Calculate widths before coding

Adding two unsigned WIDTH-bit values needs WIDTH + 1 bits to keep the carry. Adding four values needs WIDTH + 2 bits. The concatenations in the module explicitly extend operands before addition.

Without that extension, a carry can be lost before assignment to a wider output.

Constraints describe the environment

Timing analysis needs at least the clock periods and, depending on the interface, input and output delays. A clean report with incorrect constraints does not prove that the circuit will work on the board.

A false path or multicycle path must not hide a failure. It must match the real protocol behavior and have a clear justification.

A method for reading unfamiliar RTL

To understand a small module:

1. identify the interface and handshake direction;
2. locate every register and its update condition;
3. follow one item across several edges;
4. calculate the maximum width of each operation;
5. note reset, stall, and simultaneous cases;
6. compare this reading with the testbench and synthesis report.

For pipelined_sum4, the right questions are straightforward: when is an input accepted, which o_valid belongs to it, how many groups can be in flight, and what happens during reset?

Key points

• Synthesis translates code; it does not validate the specification.
• Fix a long path with architecture and correct constraints, not with #.
• Pipelining trades latency for a shorter combinational path.
• Intermediate widths must be correct before final assignment.
• Timing analysis is meaningful only with correct constraints.

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