Synthesis, timing, and RTL reading

Connect source code to the resulting circuit, read latency, and fix an overly long path.

Synthesis does not verify intent

A synthesis tool turns RTL into registers, logic, and memories. It can accept code that does not meet the specification. Simulation, lint, constraints, and report review answer different questions.

Before optimizing, check:

• the width and signedness of every calculation;
• the absence of unintended latches;
• the presence of expected registers;
• the inference of intended RAM and DSP resources;
• warnings about undriven, constant, or truncated signals.

An RTL delay does not fix timing

Writing #2 in RTL does not ask the FPGA to make a path faster. Simulation delays are not a portable synthesizable architecture.

To shorten an overly long combinational path, you can:

• add a pipeline stage;
• reorganize a calculation as a tree;
• perform less shared logic in one cycle;
• use a dedicated resource;
• revisit the frequency or protocol if the specification allows it.

Reading a small pipeline

module pipelined_sum4 #(
  parameter WIDTH = 12
) (
  input  wire                 i_clk,
  input  wire                 i_reset,
  input  wire                 i_valid,
  input  wire [WIDTH-1:0