Understanding Verilog

What Verilog is used for, how it describes a circuit, and where it fits in an FPGA project.

A language for describing hardware

Verilog is a hardware description language. A line of Verilog does not necessarily ask a processor to execute one operation after another. It can describe a logic gate, a wire, a flip-flop, or several blocks that are active at the same time.

The language is mainly used to:

• describe a digital circuit;
• verify its behavior through simulation;
• synthesize the RTL portion into FPGA resources or ASIC cells;
• review and maintain an architecture as text.

Classic Verilog was standardized in the IEEE 1364 series. It was later integrated into SystemVerilog, which is defined by IEEE 1800. This learning path uses .v files and Verilog-2001 syntax that is widely understood by FPGA tools.

A first module

A module groups an interface and its circuit. Here is a simple lock: the output is 1 when the badge is recognized and the door is closed.

module access_ok (
  input  wire i_badge,
  input  wire i_door_closed,
  output wire o_unlock
);
 
  assign o_unlock = i_badge & i_door_closed;
 
endmodule

i_badge and i_door_closed are inputs. o_unlock is the output. The assign statement describes a combinational connection that is continuously active.

If an input changes, the logical value of the output is recalculated. This is not a function called only once.

Thinking in parallel

The two outputs in the following module are independent:

module safety_flags (
  input  wire i_overtemp,
  input  wire i_fan_fault,
  input  wire i_power_good,
  output wire o_shutdown,
  output wire o_ready
);
 
  assign o_shutdown = i_overtemp | i_fan_fault;
  assign o_ready    = i_power_good & ~o_shutdown;
 
endmodule

The two assign statements describe two pieces of logic that exist at the same time. Their order in the file does not create an execution order.

The second expression does depend on o_shutdown. This dependency comes from the circuit being described, not from the position of the lines.

Simulation and synthesis

Simulation runs a model so that its outputs can be observed in different situations. It helps find a logic error before a board is programmed.

Synthesis turns compatible RTL into gates, flip-flops, memories, and other resources. Not everything that can be simulated is synthesizable. For example, a #10 delay is useful in some testbenches, but it does not create an exact physical delay in an FPGA by itself.

A simple flow looks like this:

1. write the requirements and interface;
2. describe the RTL;
3. verify the behavior;
4. synthesize the circuit;
5. place and route the resources;
6. generate and load the bitstream.

The test module

The circuit being checked is often called the DUT, for Design Under Test. Another module applies inputs and checks its outputs.

The DUT should remain separate from test code. Delays, display messages, and stimulus scenarios normally belong in the testbench, not in RTL intended for synthesis.

Verilog and VHDL

Verilog and VHDL can both describe RTL. Verilog is generally more compact and more permissive. That flexibility makes vector widths and signed values especially important.

Choosing a language does not replace circuit design. In both cases, you must understand combinational logic, flip-flops, clocks, resets, latency, and timing constraints.

Key points

• Verilog describes a circuit, not a program executed by a CPU.
• Several statements can represent hardware that is active in parallel.
• Simulation checks a model; synthesis builds a hardware representation.
• RTL and testbench code do not have the same constraints.
• This learning path uses Verilog-2001 syntax in .v files.

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