Understanding Verilog
What Verilog is used for, how it describes a circuit, and where it fits in an FPGA project.
A language for describing hardware
Verilog is a hardware description language. A line of Verilog does not necessarily ask a processor to execute one operation after another. It can describe a logic gate, a wire, a flip-flop, or several blocks that are active at the same time.
The language is mainly used to:
- describe a digital circuit;
- verify its behavior through simulation;
- synthesize the RTL portion into FPGA resources or ASIC cells;
- review and maintain an architecture as text.
Classic Verilog was standardized in the IEEE 1364 series. It was later integrated into SystemVerilog, which is defined by IEEE 1800. This learning path uses .v files and Verilog-2001 syntax that is widely understood by FPGA tools.
A first module
A module groups an interface and its circuit. Here is a simple lock: the output is 1 when the badge is recognized and the door is closed.
module access_ok (
input wire i_badge,
input wire i_door_closed,
output wire o_unlock
);
assign o_unlock = i_badge & i_door_closed;
endmodulei_badge and i_door_closed are inputs. is the output. The statement describes a combinational connection that is continuously active.