Describing combinational logic

Use assign and always @* to produce an output that depends only on the current inputs.

What a combinational circuit is

A combinational circuit does not keep state. For a given input combination, its outputs always have the same value after the physical propagation delay.

Multiplexers, decoders, and adders are common examples. In Verilog, they can be described with a continuous assignment or a combinational procedural block.

The continuous assign statement

assign works well for a short expression. Its target is a net, usually declared as wire.

module alarm_logic (
  input  wire i_smoke,
  input  wire i_overtemp,
  input  wire i_service_mode,
  output wire o_alarm
);
 
  assign o_alarm = (i_smoke | i_overtemp) & ~i_service_mode;
 
endmodule

The expression is continuously active. When an input changes, the simulation recalculates o_alarm.

Several continuous assignments describe several logic paths in parallel: