1µs Tick Generator

Intermediate

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01General Operation

The module generates a single-cycle pulse every microsecond. The system clock period is configurable via the g_MAIN_CLK_PER generic (in nanoseconds).

Reset is synchronous and active-high.

Generic g_MAIN_CLK_PER (default 10 ns for 100 MHz)
Synchronous active-high reset

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_rst`	Input	1 bit	Synchronous active-high reset
`o_tick_1us`	Output	1 bit	1-cycle pulse every 1µs

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