Chargement…
Chargement…
On rising edge based on i_mode:
00: hold01: shift right, i_sin enters at MSB10: shift left, i_sin enters at LSB11: parallel load from i_dataReset clears register to "0000".
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | Clock |
i_reset | Input | 1 bit | Active-high async reset |
i_mode | Input | 2 bits | Mode: 00=hold, 01=shift right, 10=shift left, 11=load |
i_sin | Input | 1 bit | Serial input (for shift) |
i_data | Input | 4 bits | Parallel data |
o_q | Output | 4 bits | Register content |