Iterative Unsigned Divider

The circuit uses restoring binary division. It processes one dividend bit per cycle instead of using a large combinational divider.

Behaviour

• An i_start pulse is accepted only while o_ready='1'.
• i_dividend and i_divisor are captured at start.
• A valid division takes exactly eight calculation cycles.
• o_done pulses for one cycle when o_quotient and o_remainder are ready.
• If the divisor is zero, o_divide_by_zero and o_done pulse without starting the eight iterations. The quotient is 0 and the remainder equals the dividend.
• The active-high asynchronous reset immediately cancels an operation in progress.

On each iteration:

1. shift the partial remainder and bring in the dividend most-significant bit;

2. compare that extended remainder with the divisor;

3. subtract the divisor when the comparison succeeds;

4. shift the quotient and insert the resulting bit;

5. shift the dividend toward the next bit.

After eight iterations, quotient and remainder must satisfy dividend = quotient * divisor + remainder, with remainder < divisor.