LUTs, flip-flops, block RAM, DSP, interconnects - the physical resources of a modern FPGA.
An FPGA provides logic resources and programmable connections. Its configuration selects their functions and connects them into a circuit. Loading another configuration changes that circuit after manufacture.
Calculate and store state
A LUT (look-up table) stores a function's truth table. In AMD/Xilinx 7-series devices, a six-input LUT contains 2⁶ configuration bits and can produce any Boolean function of six variables.
=
64
Manufacturers organize their resources differently:
Resource
AMD/Xilinx 7-series
Altera Cyclone V
Combinational logic
6-input LUT
Adaptive fracturable LUT within an ALM
Grouping
8 LUTs per CLB
10 ALMs per LAB
Registers
16 flip-flops per CLB
4 registers per ALM
D flip-flops store values between clock edges. In the 7-series architecture, a CLB (configurable logic block) groups eight LUTs and sixteen flip-flops. Dedicated carry chains speed up operations such as addition and counting. These quantities describe this architecture rather than all FPGAs.
Use memories and DSP blocks
BRAMs are embedded memories with fixed block sizes. In 7-series devices, common sizes include 18 and 36 kbits. Suitable coding patterns let synthesis recognize a memory:
-- Simple-port BRAM automatic inferencearchitecture rtl of bram_sp is type t_mem is array(0 to 255) of std_logic_vector(7 downto 0); signal r_mem : t_mem;begin process(i_clk) begin if rising_edge(i_clk) then if i_we = '1' then r_mem(to_integer(unsigned(i_addr))) <= i_data; end if; o_data <= r_mem(to_integer(unsigned(i_addr))); end if; end process;end architecture rtl;
Property
What to check
Size
Family-dependent; 18 or 36 kbits in 7-series
Block count
Depends on the device part number
Ports
Single port, simple dual port or true dual port, depending on configuration
Read
Synchronous in this example; optional registers add latency
Inference depends on access mode, options and target device. Check the report to confirm that the memory actually uses BRAM.
DSP blocks provide dedicated multiplication and MAC (multiply-accumulate) circuitry. A DSP48 can calculate P = A × B + C, among other operations. Its latency depends on enabled pipeline registers: producing one result per cycle does not imply one-cycle latency.
Uses include FIR and IIR filters, correlators, FFTs and image processing. Synthesis can use these blocks when the VHDL operations and widths match the available resources.
Connect the circuit to the board
Configurable I/O must comply with its bank voltage and supported standard:
Interface or resource
Use
LVCMOS 3.3 V / 1.8 V
GPIO with a compatible bank
LVDS
Differential signals
SSTL
Compatible memory interfaces
SERDES / transceivers
Serialization; PCIe needs suitable transceivers
Pin and I/O-standard constraints belong in the XDC file:
Inside the FPGA, a programmable network connects resources. The routing tool selects connections after placement. Their delays often limit maximum frequency, so the same description can perform differently across devices and constraints.
These families provide some architectural context: