Static Timing Analysis (STA)

A correct result must also arrive on time. Simulation checks values; static timing analysis (STA) checks path delays using clocks, input and output constraints, and justified exceptions.

Understand setup and hold

Setup requires data to remain stable for a minimum time before the capture edge. Changing too close to that edge can cause incorrect capture or metastability. STA therefore checks the latest arrival using maximum path delay.

Hold requires stability for a minimum time after the edge. New data arriving too early can disturb the captured value. STA checks the earliest arrival using minimum path delay.

A hold violation often requires added path delay. Lowering frequency generally does not solve it, because the problem occurs around the same capture edge.

Read the margins

Slack is the remaining margin after clock delays, setup or hold requirements and uncertainties are included:

Positive slack meets the constraint; negative slack indicates a violation. Zero sits exactly on the limit.

The diagram shows a 6 ns setup shortfall and 1 ns hold margin. Improve setup by reducing the combinational path, adding a pipeline stage or adjusting the target frequency.

Find the cause in the report

After placement and routing, the report uses implemented resource and connection delays:

Inspect the worst paths: start and end registers, logic depth and the contribution of routing. Correct the cause, then review the margins.

Check warnings and unconstrained paths as well. A clean report says nothing about a path excluded from analysis. Exceptions must reflect actual circuit operation; set_false_path should not conceal a critical path.

Distinguish timing from clock domain crossings

Excluding paths between asynchronous clocks from STA does not replace a synchronizer. Check the circuit that carries signals from one clock domain to the other. Use a synchronization chain where the signal allows it, or a handshake or asynchronous FIFO for more complex transfers. A timing report with no violations cannot confirm that the crossing is reliable.

In Vivado, use report_cdc (AMD UG835) to examine crossing structures. The AMD UG949 CDC guide explains which circuits to use. For asynchronous clock groups, see UG903. In Quartus, synchronization-chain analysis is described in the Altera metastability and MTBF reporting guide.

Practice a clock domain crossing

The multi-clock AXI4-Stream pipeline carries a stream from 100 MHz to 150 MHz through a Clock Converter and FIFO. Use the diagram validator to check interfaces, clocks and resets. This check does not measure STA margins or physical crossing reliability; those need the implementation and CDC reports described above.

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