Using Vivado block design and vendor IPs to build SoC-based FPGA designs.
In a Block Design, you connect hardware-block interfaces. IP can come from the Vivado catalog or contain your own RTL. The graphical view describes connections while each block retains its internal logic.
On a PYNQ-Z2, two AXI GPIO blocks let the processor read buttons and drive LEDs through AXI-Lite registers.
Build the processor connection
Create the project for the board or device, then open Create Block Design.
Add Zynq7 Processing System and apply board settings with .
Run Block Automation
Add two AXI GPIO blocks named LEDs and BUTTONs.
Match their widths to the board signals, set buttons as inputs and LEDs as outputs, then expose GPIO ports.
Run Run Connection Automation for AXI. Review clock, reset and interconnect connections.
Assign each IP a separate range in Address Editor.
Run Validate Design, create the HDL wrapper and check pin constraints before synthesis and implementation.
The PS initiates accesses from its master interface. Each GPIO responds through its slave interface S_AXI, and the interconnect selects the destination by address. Software must use the ranges assigned in the design.
AXI BRAM adds processor-accessible storage in the PL. Include it when the application needs that storage; GPIO blocks already have their own registers.
Integrate your own block
Define ports and registers before packaging the block with Create and Package New IP. An AXI4-Lite slave interface gives the processor access to a controlled peripheral's registers.
A direct RTL connection is enough when buttons only need to drive LEDs. AXI becomes useful when software must read inputs or choose outputs.
After a change, run Validate Design to check parameters and connections. Complement that check with behavioral simulation.