Understand the Zynq processing system and programmable logic, how to partition a design between PS and PL, and how both sides communicate over AXI.
A Zynq combines a processor system, the PS, with programmable logic, the PL, on one chip. Software runs on the processor; RTL becomes circuitry in the PL.
Zynq-7000 combines a dual-core ARM Cortex-A9 with a 7-series FPGA architecture. Zynq UltraScale+ MPSoC includes Cortex-A53 and Cortex-R5 cores while keeping the PS–PL split.
Choose where each function runs
The PS suits operating systems, files, network protocols and decision-heavy algorithms. The PL suits custom interfaces, parallel stream processing and deterministic timing requirements.
Integration can reduce external transfers, latency, power, board area and component count compared with separate CPU and FPGA devices. The benefit depends on the application. Shared DDR lets software prepare buffers for hardware processing without a slow external link.
This arrangement is useful in industrial vision, software-defined radio, robotics, fast acquisition and motor control. A software-only requirement may suit a simpler microcontroller; an entirely hardware-based pipeline may need only an FPGA.
PS and PL resources
The hard-wired Zynq-7000 PS includes:
Element
Role
CPU
Two ARM Cortex-A9 cores running software
Caches and internal memory
L1/L2 caches and On-Chip Memory
DDR controller
Access to external DDR without consuming FPGA logic
Peripherals
Ethernet, USB, UART, SPI, I2C, GPIO, timers, DMA…
Software environment
Bare-metal application, RTOS, or Linux
It can boot before PL configuration. Its peripherals use MIO pins directly or pass through EMIO and the PL for routing or custom adaptation.
The PL provides LUTs, flip-flops, BRAM, DSP blocks and clock resources. It hosts synthesized VHDL or Verilog, vendor IP and custom IP. Operations run in parallel with circuit-defined latency. Full reconfiguration is available, with partial reconfiguration on compatible architectures and flows.
Hardware/software partitioning starts from the requirements:
Requirement
Preferred side
User interface, networking, files, configuration
PS
Sequential algorithm with many branches
PS
Parallel processing of a continuous stream
PL
Custom protocol or nanosecond-level timing
PL
Acceleration of an expensive function
PS for control, PL for computation
In an industrial camera, the PS may manage Linux, Ethernet and configuration. The PL receives pixels, filters them through a pipeline and writes frames to DDR. Two execution models contribute to one application.
Arrange PS–PL communication
AXI belongs to ARM's AMBA family. A master initiates a transaction and a slave responds. Port names describe the owning block's perspective: S_AXI_HP on the PS receives accesses from a master in the PL.
Names vary by generation, but roles remain similar:
Interface
Typical initiator
Use
AXI GP / AXI HPM
PS → PL
Read and write an IP's control registers
AXI GP slave
PL → PS
PL access to the PS address space for moderate-bandwidth needs
AXI HP / HPC
PL → PS and DDR
High-throughput transfers, often using DMA
AXI ACP / ACE / coherent HPC
PL → PS caches
Coherent data sharing with processor caches
EMIO
PS ↔ PL
Route GPIO, UART, SPI, or I2C signals; this is not an AXI bus
This view represents Zynq UltraScale+ MPSoC: its APU, RPU and HPC ports identify that generation.
Separate control from data movement. AXI-Lite lets the CPU write parameters, start an IP and read status. DMA and a high-performance port move blocks between PL and DDR without CPU copies of every word. A controlled IP occupies a range in the processor's address space:
// Bare-metal example: AXI-Lite registers of an IP in the PLXil_Out32(IP_BASEADDR + CONTROL_OFFSET, START_MASK);while ((Xil_In32(IP_BASEADDR + STATUS_OFFSET) & DONE_MASK) == 0) { // The CPU can also wait for an interrupt instead of polling the register.}
Provide an interrupt to the PS controller for completion or errors, along with consistent clocks and resets. Use appropriate CDC synchronization or an asynchronous FIFO between different clock domains. For DMA-shared buffers, handle cache coherency or explicit maintenance.
Use the AMD UG949 CDC guide to choose a crossing structure for a signal or data transfer.
Follow system boot
After reset, the PS BootROM loads the first program from the selected medium, such as QSPI or SD. That program initializes resources including clocks and DDR, may configure the PL, then launches the application, U-Boot or Linux according to the boot chain.
FPGA configuration is therefore part of a wider startup process. It can occur during boot or later under PS control.
Criterion
Standalone FPGA
Microcontroller
Zynq SoC
Software and OS
Limited without an added processor
Bare metal or RTOS, sometimes Linux
Bare metal, RTOS, or Linux
Deterministic parallelism
Excellent
Limited
Excellent in the PL
High-level peripherals
IP must be integrated
Usually integrated
Integrated in the PS
Design complexity
Hardware
Usually low
Hardware and software
Typical use
Pure hardware pipeline or interface
Mostly software control
Software control plus hardware acceleration
Guided SoC project-creation exercises are planned for Club members, with project-creation tutorials also planned for everyone.