From VHDL Code to Hardware

How your VHDL code becomes FPGA hardware: synthesis, implementation, and bitstream.

The Complete Design Flow

Step 1: Synthesis

Synthesis translates your VHDL into a network of logic gates (netlist).

What the synthesizer does

Example

-- VHDL code
o_y <= (i_a AND i_b) OR (NOT i_c);

Will be synthesized into a LUT-3 with the appropriate truth table.

-- VHDL code
process(i_clk)
begin
  if rising_edge(i_clk) then
    r_data <= i_data;
  end if;
end process;

Will be synthesized into a D flip-flop with i_data on the D input and r_data on Q.

Step 2: Technology Mapping

The abstract netlist is mapped onto the FPGA's physical resources.

The synthesizer chooses to use:

• LUTs for combinational logic
• D flip-flops for registered logic
• BRAM for memories (if size is sufficient)
• DSPs for multiplications

You can influence these choices with synthesis attributes:

-- Force to BRAM (Xilinx)
attribute ram_style : string;
attribute ram_style of r_mem : signal is "block";
 
-- Force to distributed registers
attribute ram_style of r_mem : signal is "distributed";

Step 3: Placement

Logic resources are assigned to physical locations on the FPGA.

Placement influences:

• Maximum frequency (long signals = slower)
• Power consumption
• Resource utilization

You can constrain placement for timing reasons:

# Placement constraint (Xilinx XDC)
set_property LOC SLICE_X0Y0 [get_cells r_counter_reg[0]]

Step 4: Routing

Interconnects between placed resources are configured.

Routing is often the timing bottleneck. Signals traversing many interconnect resources introduce delays.

Static Timing Analysis (STA)

The tool performs static timing analysis to verify that all paths meet constraints.

Data path:
FF_src → [combo logic + routing] → FF_dst
 
Setup time violation if:
  Tclk_to_Q + T_logic + T_route > Tperiod - Tsetup

Step 5: Bitstream

The bitstream is the configuration file that programs the FPGA.

# Xilinx: .bit file
vivado -mode batch -source program.tcl
 
# Intel: .sof / .rbf file
quartus_pgm -m jtag -o "p;output.sof@1"

Configuration Memory Types

On most development kits, SRAM configuration is loaded via JTAG from the synthesis tool. Production uses external SPI Flash.

What VHDL CANNOT Synthesize

Synthesis Best Practices

1. Test in simulation first — do not synthesize untested code
2. Follow templates — D flip-flop, RAM, FSM (synthesizer recognizes them)
3. Avoid latches — use default values in combinational processes
4. Constrain timing — SDC/XDC file with create_clock
5. Check reports — Timing Summary, Utilization, Synthesis Log

# Minimum timing constraint (Xilinx XDC)
create_clock -period 10.000 -name sys_clk [get_ports i_clk]