Chargement…
How your VHDL code becomes FPGA hardware: synthesis, implementation, and bitstream.
VHDL describes the circuit; tools turn it into placed and connected FPGA resources. The bitstream contains the configuration produced at the end of this flow.
Synthesis analyzes RTL behavior and builds a netlist. These are common mappings:
| VHDL Construct | Inferred Hardware |
|---|
AND, OR, NOT | Logic gates in LUTs |
if rising_edge(i_clk) | D flip-flop |
case on signal | MUX or LUT |
array of signals | Registers or BRAM |
* (multiplication) | DSP or LUTs |
when/select | MUX |
This expression combines three inputs and can fit in a LUT with at least three inputs:
-- VHDL code
o_y <= (i_a AND i_b) OR (NOT i_c);This process describes a D flip-flop with i_data on D and r_data on Q. For a vector, it describes a bank of flip-flops:
-- VHDL code
process(i_clk)
begin
if rising_edge(i_clk) then
r_data <= i_data;
end if;
end process;Technology mapping adapts the netlist to the target: LUTs for combinational logic, flip-flops for stored values, BRAMs for suitable memories and DSP blocks for compatible calculations. Memory size and access mode affect inference.
Attributes can guide these choices within the tool and device capabilities:
-- Force to BRAM (Xilinx)
attribute ram_style : string;
attribute ram_style of r_mem : signal is "block";
-- Force to distributed registers
attribute ram_style of r_mem : signal is "distributed";Placement assigns resources to physical locations. It affects connection lengths, frequency, power and the arrangement of used resources. A placement constraint can address a specific requirement:
# Placement constraint (Xilinx XDC)
set_property LOC SLICE_X0Y0 [get_cells -hier -filter {NAME == r_counter_reg[0]}]Routing then selects interconnections. Long paths or many routing resources can form the critical path. STA checks delays against constraints; this relation illustrates a simple setup path without clock skew:
Data path:
FF_src → [combo logic + routing] → FF_dst
Setup time violation if:
Tclk_to_Q + T_logic + T_route > Tperiod - TsetupUse Timing Summary, Utilization and Synthesis Log to understand the result. At minimum, declare the clock in XDC or SDC constraints:
# Minimum timing constraint (Xilinx XDC)
create_clock -period 10.000 -name sys_clk [get_ports i_clk]Formats and commands depend on the tools. Vivado uses .bit, among other formats; Quartus uses .sof or .rbf. The commands below load a configuration, with an appropriate programming script for Vivado:
# Xilinx: .bit file
vivado -mode batch -source program.tcl
# Intel: .sof / .rbf file
quartus_pgm -m jtag -o "p;output.sof@1"| Type | Persistence | Usage |
|---|---|---|
| Internal SRAM | Volatile (lost on power-off) | Development |
| External Flash | Non-volatile | Production |
| EEPROM | Non-volatile | Small FPGAs |
Development boards often allow SRAM configuration through JTAG. External SPI flash can supply it at startup in development or production.
Not every VHDL construct useful in simulation describes synthesizable hardware:
| Construct | Simulation | Synthesis |
|---|---|---|
wait for 10 ns | ✓ | ✗ |
Runtime real type | ✓ | Generally unsupported; constant calculations may work |
Files (textio) | ✓ | ✗ |
assert | ✓ | Ignored or limited depending on the tool |
after in an assignment | ✓ | Delay ignored or construct rejected, depending on the tool |
Simulate before implementation, use recognized flip-flop, RAM and FSM patterns, then inspect the reports. In combinational processes, assign every output in every case to avoid unintended latches.
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