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4-bit Johnson counter: shift register where the complement of the leaving LSB is fed back into the MSB. Produces 2N = 8 distinct states for a 4-bit register.
Behaviour:
i_rst='1', synchronous): o_q ← "0000".i_clk: right shift, o_q(3) ← NOT o_q(0) (inverted feedback).Generated sequence (8 states before wrap):
0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000 → ...
*Synchronous active-high reset (sampled on the rising edge).*
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_rst | Input | 1 bit | Active-high synchronous reset |
o_q | Output | 4 bits | Counter output |