UART - Top-level assembly

Instantiate the four provided components (uart_clk_div, uart_debouncer, uart_tx, uart_rx) to build the uart top-level. The clock-divider output w_clk_en feeds both TX and RX FSMs. The debouncer output w_rxd_deb is the filtered RX signal that enters uart_rx. Propagate the generics g_PARITY_TYPE and g_CLK_FREQ/g_BAUD_RATE to the relevant sub-modules. Follow the project naming conventions (i_, o_, w_, r_, P_, c_, g_).