TESTBENCH

Verify flags and data order with two independent clocks.

FIFO EmptyFIFO Full

Testbench: Streaming register slice

Verify throughput, retention under backpressure and no data loss.

ValidReady

Testbench: Fair arbiter under backpressure

Verify fairness, request preservation and removal of a blocked client.

FairnessBackpressure

Testbench: UART receiver

Verify sampling, start/stop bits and framing error reporting.

SamplingFraming Error

Testbench: SPI memory controller

Verify command-address-data sequencing and return to idle.

ProtocolLatency

Testbench: Pipelined multiplier

VHDL

Verify latency, one-transaction-per-cycle throughput and signed boundaries.

Complete Testbench: SPI memory controller

Testbench: Two-output packet router

VHDL

Verify routing, conservation and blocking when an output is full.

Complete Testbench: Pipelined multiplier

Testbench: Credit-based FIFO

VHDL

Verify throughput, credit consumption and no send without credit.

Complete Testbench: Two-output packet router

Testbench: Pulse synchronizer

VHDL

Verify that a pulse is captured once despite different clocks.

Complete Testbench: Credit-based FIFO

Testbench: Packet assembler

VHDL

Verify length, checksum, backpressure and separation of two packets.