AXI Protocol

The AXI (Advanced eXtensible Interface) protocol by ARM: write/read channels, burst transfers and handshake.

What is AXI?

The AXI (Advanced eXtensible Interface) protocol is an interconnect protocol developed by ARM for its AMBA architectures. It standardizes high-performance communication between hardware components in a SoC (System on Chip).

Its two key strengths:

  • Performance: designed for high-frequency data exchange
  • Handshake: reliable synchronization via independent VALID/READY signals

AXI is split into two parts: addresses and data. This requires a significant number of signals.

Write

AXI Write signals

A write transaction requires 13 signals across three channels: Write Address (AW), Write Data (W), and Write Response (B).

Writes can be done with or without burst. Burst mode sends a single start address followed by successive data beats — saving time when addresses are contiguous.

AXI Write diagram

Write transaction sequence:

  1. Place the address on AWADDR, set data width (AWSIZE) and transaction length (AWLEN).
  2. Assert AWVALID in parallel and wait for AWREADY from the slave.
  3. Wait for WREADY and send data in burst with WVALID asserted.
  4. Assert WLAST on the last data beat.
  5. Check the response on BRESP (expected: OKAY).

Read

AXI Read signals

A read transaction requires 11 signals across two channels: Read Address (AR) and Read Data (R).

AXI Read diagram

Read transaction sequence:

  1. Place the address on ARADDR, set ARSIZE and ARLEN.
  2. Assert ARVALID in parallel and wait for ARREADY from the slave.
  3. Wait for RVALID and read data in burst.
  4. Watch RLAST to detect the last data beat.
  5. Check the response on RRESP (expected: OKAY).

Signal Summary

ChannelKey SignalsDirection
AW (Write Address)AWADDR, AWLEN, AWSIZE, AWVALID, AWREADYMaster → Slave
W (Write Data)WDATA, WSTRB, WLAST, WVALID, WREADYMaster → Slave
B (Write Response)BRESP, BVALID, BREADYSlave → Master
AR (Read Address)ARADDR, ARLEN, ARSIZE, ARVALID, ARREADYMaster → Slave
R (Read Data)RDATA, RLAST, RRESP, RVALID, RREADYSlave → Master

For a simplified version (no burst, no complex address management), see the AXI-Lite Protocol course.