The AXI (Advanced eXtensible Interface) protocol by ARM: write/read channels, burst transfers and handshake.
AXI divides a transaction into separate exchanges. An address, data item or response can wait on its channel while other channels continue.
Use the five channels
Channel
What it carries
Value direction
AW
Write address and burst parameters
Master to slave
W
Write data, byte mask and last-word flag
Master to slave
B
Write response
Slave to master
AR
Read address and burst parameters
Master to slave
R
Read data and response
Slave to master
On each channel, the sender presents information and asserts VALID. The receiver drives READY in the opposite direction. A transfer occurs at a rising edge where both are 1.
Assert VALID when information is available, without waiting for READY. Hold VALID and its associated information until transfer. The rule applies to addresses, data and responses alike.
The master presents AWADDR and burst parameters. AWSIZE encodes transfer size in bytes as a power of two; AWLEN gives the number of beats minus one. The address transfers through the AWVALID / AWREADY handshake.
On W, WVALID accompanies each beat. WSTRB selects bytes to write and WLAST marks the final beat. Address and data handshakes are independent, so acceptance may occur in different cycles.
Once the address and final beat have been accepted, the slave can present BRESP with BVALID. The master accepts the response with BREADY and checks its result, such as OKAY.
Receive a read burst
The master sends ARADDR, ARSIZE and ARLEN with ARVALID. After the address handshake, the slave provides beats on RDATA, each with RVALID and RRESP.
The master indicates capacity with RREADY. RLAST marks the final beat. During a stall, data and associated information remain stable until transfer.
For register control using single-beat transactions, continue with AXI4-Lite.