4x8 Register File

Intermediate

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01General Operation

Register file 4×8 bits with one synchronous write port and two independent asynchronous read ports — the canonical layout of a CPU register file.

Behaviour:

Reset (i_reset='1'): all registers ← "00000000".
Write: on the rising edge of i_clk, if i_we='1', i_wdata is stored at i_waddr.
Read port 1: o_rdata1 ← contents of i_raddr1 (combinational).
Read port 2: o_rdata2 ← contents of i_raddr2 (combinational).

*Allows reading two operands simultaneously in a single cycle. Asynchronous active-high reset.*

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	Clock
`i_reset`	Input	1 bit	Active-high async reset
`i_we`	Input	1 bit	Write enable
`i_waddr`	Input	2 bits	Write address
`i_wdata`	Input	8 bits	Write data
`i_raddr1`	Input	2 bits	Read address port 1
`i_raddr2`	Input	2 bits	Read address port 2
`o_rdata1`	Output	8 bits	Read data port 1
`o_rdata2`	Output	8 bits	Read data port 2

Chargement…