4-Stage Pipelined 5x5 Multiplier

The module performs the unsigned multiplication i_a * i_b, with two 5-bit operands and a 10-bit output.

Behaviour:

• a new operand pair may be applied every cycle;
• the matching result appears after 4 rising edges;
• once filled, the circuit produces one result per cycle;
• i_rst='1' clears all internal registers and o_y.

The read-only file mult5_non_pipeline.vhd shows the starting combinational version. Your goal is to code mult5_pipeline.vhd with pipeline registers.

The expected structure is a 4-stage pipeline:

• stage 1: compute partial products for bits i_b(0) and i_b(1), then register the partial sum;
• stage 2: add the delayed partial product for bit b(2);
• stage 3: add the delayed partial product for bit b(3);
• stage 4: add the delayed partial product for bit b(4) and register o_y.

Delayed versions of i_a and i_b must move with the partial sums. Without this alignment, the result mixes several multiplications.